1. Field of the Invention
The present invention relates to low-voltage circuits for generating broadband radio frequency (RF) pulses, and, in particular, to an RF power amplifier generating high-power pulses.
2. Description of the Related Art
Radio frequency (RF) applications increasingly employ integrated circuit (IC) technology, but, until recently, only discrete semiconductor components, or small-scale bipolar or gallium-arsenide (GaAs) ICs, could operate at RF and microwave frequencies. Metal-oxide semiconductor (MOS) technology employed for ICs may allow for operation at frequencies of a gigahertz and greater. In addition, the combination of bipolar and MOS transistors in BiCMOS technology allows for operation of ICs at even higher frequencies. Silicon-germanium (SiGe) bipolar transistors further raise the upper limit of IC operation, and experimental digital circuits operating at tens of gigahertz, previously the domain of discrete transistors and small-scale ICs, have been built.
Within the area of RF applications, wireless networking is becoming increasingly popular, though transceivers are still expensive. One technique employed for communication between transceivers in wireless networking uses short RF pulses, rather than using a traditional modulated carrier, to transfer data. For example, an RF output waveform (representing a data symbol) of a transceiver might comprise a few cycles of a sine wave at a frequency of a few gigahertz. When short RF pulses are used, the RF power is spread out over a larger frequency band than when a conventional, data-modulated carrier is employed for communication. Spreading the RF power over a larger frequency band may exhibit the advantage of permitting a large output power to meet FCC regulations.
When ICs are employed in RF applications, even though the ICs are operating at higher frequencies, the ICs are also operating at lower voltages. However, low-voltage ICs typically operate with low output power levels that are often incompatible with the power levels required for transmission.
The problems in the prior art are addressed in accordance with the principles of the present invention by a pulse power amplifier biased with a relatively low supply voltage that generates one or more pulses having a relatively large output power. The pulse power amplifier biased with a relatively low supply voltage generates one or more pulses having a relatively large output power. The pulse power amplifier provides a short pulse from a pair of pulsed input digital signals. The pulse power amplifier includes two sections, each section driving a corresponding half of a balanced-to-unbalanced (balun) transformer, to generate a portion of the output pulse. Each section receives its input digital signal at a MOS transistor which acts as a current switch for a bias current from a current source. With a relatively small voltage change in response to the input digital signal, the MOS transistor switches the bias current between itself and a transistor pair used to drive the corresponding half of the balun transformer. Such configuration may allow for a MOS circuit, which operates with a relatively low supply voltage (and low power), that is coupled to the pulse power amplifier to generate an output pulse having a relatively high output power.
According to one embodiment, the present invention is a circuit including a push-pull power amplifier configured to operate in a switching mode. The push-pull amplifier comprises a first section coupled to receive a first input signal and a second section coupled to receive a second input signal, wherein each of the first and second sections comprises a metal oxide semiconductor (MOS) transistor, a transistor pair, and a current source providing a bias current to the MOS transistor and the transistor pair, wherein the MOS transistor is coupled to the transistor pair so as to switch the bias current between the MOS transistor and the transistor pair in response to the corresponding input signal. The circuit further includes a signal combiner adapted to receive signals from the first and second sections to drive a load impedance, wherein, when the MOS transistor of the first section switches the bias current to the transistor pair, the transistor pair drives the load impedance through the signal combiner in one direction, and, when the MOS transistor of the second section switches the bias current to the transistor pair, the transistor pair drives the load impedance through the signal combiner in another direction.